1. Technical Field
Example embodiments relate generally to semiconductor integrated circuits, and more particularly to a memory test system and a memory system to perform a test efficiently.
2. Discussion of the Related Art
As memory capacity of a memory device increases, a test time for detecting failed memory cells in the memory device typically increases. Since the increased the test time raises cost of the memory device, it is desired to find a method of reducing the test time.
If a large number of failed memory cells are found in a stage of post-package recovery (PPR), there is a high probability that the errors may be due to a problem in a tester that performs the test with respect to the memory device. In this case, the good memory cells may be determined to be the bad memory cells. Repair resources such as replaced memory cells may be exhausted in the PPR stage and thus the memory cells that are defective in a normal use after the PPR stage cannot be repaired.